rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a dac8043a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/461-3113 ? analog devices, inc., 2006 12-bit serial input multiplying d/a converter functional block diagram 12-bit shift register dac reg 12 12 dac dac8043a v dd v ref ld clk sri gnd i out r fb features compact soic, and tssop packages true 12-bit accuracy 5 v operation @ <10 a fast 3-wire serial input fast 1 s settling time 2.4 mhz 4-quadrant multiply bw pin-for-pin upgrade for dac8043 standard and rotated pinout applications ideal for plc applications in industrial control programmable amplifiers and attenuators digitally controlled calibration and filters motion control systems general description the dac8043a is an improved high accuracy 12-bit multiply- ing digital-to-analog converter in space-saving 8-lead packages. featuring serial input, double buffering and excellent analog performance, the dac8043a is ideal for applications where pc board space is at a premium. improved linearity and gain error performance permit reduced parts count through the elimina- tion of trimming components. separate input clock and load dac control lines allow full user control of data loading and analog output. the circuit consists of a 12-bit serial-in/parallel-out shift regis- ter, a 12-bit dac register, a 12-bit cmos dac and control logic. serial data is clocked into the input register on the rising edge of the clock pulse. when the new data word has been clocked in, it is loaded into the dac register with the ld input pin. data in the dac register is converted to an output current by the d/a converter. co n suming only 10 a from a single 5 v power supply, the dac8043a is the ideal low power, small size, high performance solution to many application problems. the dac8043a is specified over the extended industrial (?0 c to +85 c) temperature range. dac8043a is available in a pdip package, and the low profile 1.75 mm height soic-8 surface mount packages. the dac8043afru is available for ultra-compact applications in a thin 1.1 mm tssop-8 package. code inl ?lsb 0.1 0 ?.1 0 1024 2048 3072 4096 ?.5 0.5 0.4 0.3 0.2 ?.2 ?.3 ?.4 512 1536 2560 3584 t a = +25 c, +85 c, ?0 c v dd = +5v v ref = ?0v figure 1. integral nonlinearity error vs. code
rev. b ? dac8043a?pecifications parameter symbol condition e grade f grade unit static performance resolution n 12 12 bits relative accuracy inl 0.5 1.0 lsb max differential nonlinearity dnl all grades monotonic to 12 bits 0.5 1.0 lsb max gain error 1 g fse t a = 25 c, data = fff h 1.0 2.0 lsb max t a = ?0 c, +85 c, data = fff h 2.0 2.0 lsb max gain tempco 2 tcg fs i out pin measured 5 5 ppm/ c max output leakage current i lkg data = 000 h , i out pin measured 5 5 na max t a = ?0 c, +85 c, data = 000 h , i out pin measured 25 25 na max zero-scale error 3 i zse data = 000 h 0.03 0.03 lsb max t a = ?0 c, +85 c, data = 000 h 0.15 0.15 lsb max reference input input resistance r ref absolute tempco < 50 ppm/ c 7/15 7/15 k ? min/max input capacitance 2 c ref 55 pf typ analog output output capacitance 2 c out data = 000 h 25 25 pf typ data = fff h 30 30 pf typ digital inputs digital input low v il 0.8 0.8 v max digital input high v ih 2.4 2.4 v min input leakage current i il v logic = 0 v to 5 v 0.001/ 1 0.001/ 1 a typ/max input capacitance 2 c il v logic = 0 v 10 10 pf max interface timing 2, 4 data setup t ds 10 10 ns min data hold t dh 55 ns min clock width high t ch 25 25 ns min clock width low t cl 25 25 ns min load pulsewidth t ld 25 25 ns min lsb clk to ld dac t asb 00 ns min ac characteristics 1, 2 output current settling time t s to 0.01% of full scale, ext op amp op42 1 1 s max dac glitch q data = 000 h to fff h to 000 h , v ref = 0 v 20 20 nvs max feedthrough (v out /v ref )ft v ref = 20 v p-p, data = 000 h , f = 10 khz 1 1 mv p-p total harmonic distortion thd v ref = 6 v rms, data = fff h , f = 1 khz ?5 ?5 db typ output noise density 5 e n 10 hz to 100 khz between r fb and i out 17 17 nv/ hz max multiplying bandwidth bw ? db, v out /v ref , v ref = 100 mv rms, data = fff h 2.4 2.4 mhz typ supply characteristics power supply range v dd range 4.5/5.5 4.5/5.5 v min/max positive supply current i dd v logic = 0 v or v dd 10 10 a max power dissipation p diss v logic = 0 v or v dd 50 50 w max power supply sensitivity pss ? v dd = 5% 0.002 0.002 %/% max notes 1 using internal feedback resistor r fb , see figure 19 test circuit with v ref = 10 v. 2 these parameters are guaranteed by design and not subject to production testing. 3 calculated from worst case r ref : i zse (lsb) = (r ref i lkg 4096)/v ref . 4 all input control signals are specified with t r = t f = 2 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 5 calculation from e n = 4ktrb where: k = boltzmann constant (j/ k), r = resistance ( ? ), t = resistor temperature ( k), b = 1 hz bandwidth. specifications subject to change without notice. electrical characteristics (@ v dd = 5 v, v ref = 10 v, 40 c < t a < +85 c, unless otherwise noted.)
rev. b dac8043a ? absolute maximum ratings * v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v, +8 v v ref to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v r fb to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v logic inputs to gnd . . . . . . . . . . . . . . ?.3 v, v dd + 0.3 v vi out to gnd . . . . . . . . . . . . . . . . . . . ?.3 v, v dd + 0.3 v i out short circuit to gnd . . . . . . . . . . . . . . . . . . . . . 50 ma package power dissipation . . . . . . . . . . . . . (t j m ax ?t a )/ ja thermal resistance ja 8-lead pdip package (n-8) . . . . . . . . . . . . . . . . . 103 c/w 8-lead soic package (r-8) . . . . . . . . . . . . . . . . . 158 c/w 8-lead tssop package (ru-8) . . . . . . . . . . . . . . 240 c/w maximum junction temperature (t j m ax) . . . . . . . . . 150 c operating temperature range . . . . . . . . . . 40 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin function descriptions #( * ) name function 1(7) v ref dac reference input pin. establishes dac full- scale voltage. constant input resistance versus code. 2 (8) r fb internal matching feedback resistor. connect to external op amp output. 3 (1) i out dac current output, full-scale output 1 lsb less than reference input voltage ? ref . 4 (2) gnd analog and digital ground. 5 (3) ld load strobe, level-sensitive digital input. transfers shift-register data to dac register while active low. see truth table for operation. 6 (4) sri 12-bit serial register input, data loads directly into the shift register msb first. extra leading bits are ignored. 7 (5) clk clock input, positive-edge clocks data into shift register. 8 (6) v dd positive power supply input. specified range of operation 5 v 10%. * note pin numbers in parenthesis represent the rotated pinout of the dac8043a1es and dac8043a1fs models. dac8043ae/f pin configurations 1 4 5 8 soic-8 dac8043a es/fs 1 4 5 8 tssop-8 dac8043a fru top view (not to scale) 8 7 6 5 1 2 3 4 i out gnd ld r fb v ref v dd clk sri pdip-8 dac8043a ep/fp dac8043a1e and dac8043a1f pin configuration (rotated pinout) top view (not to scale) 8 7 6 5 1 2 3 4 i out gnd ld r fb v ref v dd clk sri soic-8 dac8043a1es dac8043a1fs ordering guide caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the dac8043a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. b dac8043a ? sri clk ld sri clk ld fs zs v out data loaded msb(d11) first dac register load d11 d10 d9 d8 d6 d5 d4 d3 d2 d1 d0 d7 t ld1 t ds t dh t cl t ch t ld t s 1 lsb error band dxx t asb figure 2. timing diagram table i. control-logic truth table clk ld serial shift register function dac register function u h shift-register-data advanced one bit latched h or l l no effect updated with current shift register contents l u no effect latched all 12 bits notes u positive logic transition. the dac register ld input is level-sensitive. any time ld is logic-low data in the serial register will directly control the switches in the r-2r dac ladder. total unadjusted error ?lsb frequency 15 20 0 ?.0 1.0 10 30 ?.5 0.0 0.5 ss = 200 units t a = 25 c v dd = 5v v ref = 10v 25 5 35 figure 3. total unadjusted error histogram t ypical performance characteristics full scale tempco ?ppm/ c frequency 30 20 0 0 10 40 50 ss = 200 units t a = 40 c to +85 c v dd = 5v v ref = 10v 12 figure 4. full-scale output tempco histogram
rev. b dac8043a ? logic input voltage ?volts supply current i dd ?ma 0.1 0 0 0.2 0.5 t a = 25 c v dd = 5v 12 345 0.5 1.5 2.5 3.5 4.5 0.3 0.4 figure 5. supply current vs. logic input voltage temperature ? c i dd ? a 0.01 0.001 ?5 0.1 10 v dd = 5v v logic = 0v or v dd ?5 ?5 5 25 45 1 65 85 105 125 figure 6. supply current vs. temperature frequency ?hz i dd ? a 500 0 10k 1000 v dd = 5v v ref = 10v t a = 25 c 100k 1m 10m 100m 1k 1500 2000 3000 3500 2500 code = f55h code = 800h code = fffh figure 7. supply current vs. clock frequency frequency ?hz psrr ?db 20 10k v dd = 5v 10% 100k 1m 10m 40 60 80 100 1k figure 8. power supply rejection vs. frequency code ?decimal dnl ?lsb ?.5 1024 2048 3072 4096 ?.4 0 ?.3 ?.2 ?.1 0 0.2 0.4 0.5 v dd = 5v v ref = 10v superimposed: t a = ?0 c, +25 c, +85 c 512 1536 2560 3584 0.1 0.3 figure 9. linearity error vs. digital code opamp offset v os ? v inl ?lsb ?000 0 1000 2000 ?000 2 0 4 v dd = 5v v ref = 10v t a = 25 c ? ? figure 10. linearity error vs. external op amp v os
rev. b dac8043a ? 20mv v dd = 5v v ref = 10v f clk = 2.5mhz code: 7ff h to 800 h v out (10mv/div) time ?200ns/div ld (5v/div) figure 11. midscale transition performance 5v 5v v dd = 5v v ref = 10v t a = 25 c clk (5v/div) time ?1 s/div v out (5v/div) figure 12. large signal settling time frequency ?hz 0 12 24 36 48 60 72 84 96 1k 10k 100k 1m 10m all bits on data bits "on" (all other data bits "off") b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 (msb) b 11 (lsb) b 0 attenuation ?db 108 100 all bits off figure 13. reference multiplying bandwidth vs. fre- quency and code | v ref | ?volts inl ?lsb 0 0 10 ?.5 ?.25 0.5 0.25 v dd = 5v t a = 25 c 5 figure 14. linearity error vs. reference voltage hours of operation at 150 c nominal change in voltage ?mv 0 1.0 code = 000 h code = fff h sample size = 50 0 0.2 0.4 0.6 0.8 1.2 100 200 300 400 500 600 figure 15. long-term drift accelerated by burn-in ?5 10 0.0018 1k 10k 100k thd ?% 100 0.0032 0.0056 0.010 0.018 0.032 ?0 ?5 ?0 ?5 ?0 v ref = 4v p-p output op amp: op42 thd ?db frequency ?hz figure 16. thd vs. frequency
rev. b dac8043a ? parameter definitions integral nonlinearity (inl) this is the single most important dac specification. adi mea- sures inl as the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. it is expressed as a percent of full-scale range or in terms of lsbs. refer to analog devices data reference manual for additional digital-to-analog converter definitions. interface logic information the dac8043a has been designed for ease of operation. the timing diagram, figure 2, illustrates the input register loading sequence. note that the most significant bit (msb) is loaded first. once the 12-bit input register is full, the data is transferred to the dac register by taking ld momentarily low. digital section the dac8043a? digital inputs, sri, ld , and clk, are ttl compatible. the input voltage levels affect the amount of cur- rent drawn from the supply; peak supply current occurs as the digital input (vin) passes through the transition region. see the supply current vs. logic input voltage graph located in the typical performance characteristics curves. maintaining the digital input voltage levels as close as possible to the supplies, vdd and gnd, minimizes supply current consumption. the dac8043a? digital inputs have been designed with esd resis- tance incorporated through careful layout and the inclusion of input protection circuitry. figure 17 shows the input protection diodes and series resistor; this input structure is duplicated on each digital input. high voltage static charges applied to the inputs are shunted to the supply and ground rails through for- ward biased diodes. these protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions. v dd ld , clk, sri gnd 5k figure 17. digital input protection general circuit information the dac8043a is a 12-bit multiplying d/a converter with a very low temperature coefficient. it contains an r-2r resistor ladder network, data input and control logic, and two data registers. the digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12-bit shift regis- ter and then transferred, in parallel, to the 12-bit dac register. the analog portion of the dac8043a contains an inverted r- 2r ladder network consisting of silicon-chrome, highly-stable (50 ppm/ c) thin-film resistors, and twelve pairs of nmos current-steering switches, see figure 18. these switches steer binarily weighted currents into either i out or gnd; this yields a constant current in each ladder leg, regardless of digital input code. this constant current results in a constant input resis- tance at v ref equal to r. the v ref input may be driven by any reference voltage or current, ac or dc that is within the limits stated in the absolute maximum ratings. 10k s1 20k s2 20k 10k s3 20k 10k s12 20k 20k * * 10k bit 1 (msb) bit 2 bit 3 bit 12 (lsb) r feedback v ref i out gnd digital inputs (switches shown for digital inputs "high") *these switches permanently "on" figure 18. simplified dac circuit the twelve output current steering nmos fet switches are in series with each r-2r resistor. to further ensure accuracy across the full temperature range, permanently ?n?mos switches were included in series with the feedback resistor and the r-2r ladder? terminating resistor. figure 18 shows the location of the series switches. during any testing of the resistor ladder or r feedback (such as incoming inspection), v dd must be present to turn ?n?these series switches. dynamic performance output impedance the dac8043a? output resistance, as in the case of the output capacitance, varies with the digital input code. this resistance, looking back into the i out terminal, may be between 10 k ? (the feedback resistor alone when all digital inputs are low) and 7.5 k ? (the feedback resistor in parallel with approximate 30 k ? of the r-2r ladder network resistance when any single bit logic is high). static accuracy and dynamic performance will be affected by these variations. applications information in most applications, linearity depends upon the potential of the i out and gnd pins being at the same voltage potential. the dac is connected to an external precision op amp inverting input. the external amplifiers noninverting input should be tied directly to ground without the usual bias current compensating resistor. (see figures 19 and 20.) the selected amplifier should have a low input bias current and low drift over temperature. the amplifiers input offset voltage should be nulled to less than 200 microvolts (less than 10% of 1 lsb). all grounded pins should tie to a single common ground point to avoid ground loops. t he v dd power supply should have a low noise level with ad equate bypassing. it is best to operate the dac8043a from the analog power supply and grounds. unipolar 2-quadrant multiplying the most straightforward application of the dac8043a is in the 2-quadrant multiplying configuration shown in figure 19. if t he reference input signal is replaced with a fixed dc voltage
rev. b dac8043a ? c00272??/06 (b) r eference, the dac output will provide a proportional dc voltage output according to the transfer equation: v out = d /4096 v ref where d is the decimal data loaded into the dac register and v ref is the externally applied reference voltage source. v ref i out gnd op77 2r r r fb v ac v dd r fb 10v p v out 2r digital inputs omitted for clarity 10pf figure 19. unipolar (2-quadrant) operation bipolar 4-quadrant multiplying figure 20 shows a suggested circuit to achieve 4-quadrant mul- tiplying operation. the summing amplifier multiplies v out1 by 2, and offsets the output with the reference voltage so that a midscale digital input code of 2048 places v out2 at zero volts. the negative full-scale voltage will be v ref when the dac is loaded with all zeros. the positive full-scale output will be ?v ref ?1 lsb) when the dac is loaded with all ones. thus the digital coding is offset binary. the voltage output transfer equation for various input data and reference (or signal) values follows: v out 2 = ( d /2048 ?1) v ref where d is the decimal data loaded into the dac register and v ref is the externally applied reference voltage source. precision resistors will be necessary to avoid ratio errors. other- wise trimming will be required to achieve full accuracy specifica- tions available from the dac8043a device. see the various analog devices digital potentiometer products for automated trimming solutions (e.g., the ad5204 for low voltage applica- tions or the ad7376 for high voltage applications). (0v to ? ref ) v ref i out gnd 2r r r fb v ac v dd r fb 10v p v out1 2r digital inputs omitted for clarity op213 10k op213 v out2 20k 20k 10pf figure 20. bipolar (4-quadrant) operation 8-lead standard small outline package [soic_n] (r-8) s-suffix dimensions shown in millimeters and (inches). 8-lead plastic dual in-line package [pdip] (n-8) dimensions shown in inches and (millimeters). 8-lead thin shrink small outline package [tssop] (ru-8) dimensions shown in millimeters. outline dimensions
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